1. Technical Field
The present invention relates to a power semiconductor module.
2. Background Art
Some flat semiconductor devices seek to achieve downsizing and reduced impedance of the wiring by connecting the electrodes to external circuits by pressure welding. Such flat semiconductor devices are described in Patent Document 1, for example.
FIG. 8 shows an example of a flat semiconductor device in a cross-sectional view. A power semiconductor module 101 is equipped with a metal electrode plate 102. Semiconductor chips 103 are electrically and physically connected on the electrode plate 102. In the illustrated example, the semiconductor chips 103 are power MOSFETs, and are provided in a plurality of units on the electrode plate 102. A drain electrode formed on the reverse surface of each of the semiconductor chips 103 is joined to the electrode plate 102 by a joining material not shown in the diagram, such as solder.
In addition to the semiconductor chips 103, a multilayer substrate 104 is joined on the electrode plate 102. The multilayer substrate 104 is constituted by: an insulating plate 141, a metal plate 142, and a circuit plate 143. The metal plate 142 is provided on one surface of the insulating plate 141 and joined to the multilayer substrate by a joining material not shown in the diagram, such as solder. The circuit plate 143 is provided on the other surface of the insulating plate 141 and forms prescribed circuits.
Additionally, the bottom surface of a metal block 110 is electrically and physically connected to the circuit plate 143 of the multilayer substrate 104. The top surface of the metal block 110 protrudes out of a cover 111, and also serves as an electrode of the power semiconductor module 101. The semiconductor chips 103 and the multilayer substrate 104 are sealed by a sealing material 108, such as a thermosetting resin.
In order to electrically connect the semiconductor chip 103 and the multilayer substrate 104, a source electrode formed on the front surface of the semiconductor chip 103 is connected to the circuit plate 143 by bonding wiring 107. Additionally, a gate electrode formed on the front surface of the semiconductor chip 103 is connected to the circuit plate 143 by the bonding wiring 107.
The power semiconductor module 101 shown in FIG. 8 is not independently insulated from the outside, and therefore requires a device on which the power semiconductor module 101 is installed to provide an insulating function to the power semiconductor module 101. In other words, the power semiconductor module 101 is a non-insulated power semiconductor module.
When current is passed through the conventional power semiconductor module 101, heat generated from the semiconductor chips 103 is predominantly dissipated through the electrode plate 102. The reason for this is that heat dissipation from the front surfaces of the semiconductor chips 103 on the side opposite to the electrode plate 102 contributes very little to the overall heat dissipation, due to the large thermal resistance of the sealing material 108 and the bonding wiring 107. This has limited the extent to which heat is dissipated from the semiconductor chips 103.
Flat type welding structure packages are designed to establish a contact between an electrode layer on the top surface of a semiconductor element provided on a substrate and a contact terminal. In one such flat type welding structure package, a thermal stress mitigating member is inserted between the contact terminal and the semiconductor element (Patent Document 2). The power semiconductor module described in Patent Document 2 is able to dissipate heat generated by the semiconductor element from not only the substrate but also the contact terminal, and is therefore considered to be more advanced than the power semiconductor module of Patent Document 1.
However, with respect to the power semiconductor module described in Patent Document 2, linear load from the contact terminal is exerted on the semiconductor element when the power semiconductor module is undergoes pressure welding, thus posing the risk that excessive load may be applied to the semiconductor element.